高通徵才訊息Opening from Qualcomm Intern, Digital Design Engineer

 

 

 

Job description:

 

1. Participate in whole ASIC flow, including development of micro architecture specification, RTL implementation, design verification, synthesis, APR, CTS, timing closure, power estimation and DFT.

 

2 .Support the RTL2GDS design flow with physical design team.

 

3. Study and optimized chip performance, power and area.

 

4. Support validation and software team.

 

5. Support post-silicon bring up and test.

 

 

 

Requirement:

 

*** Able to commit at least 3 months internship and work 20 hours per week. ***

 

1. Familiar with C, Verilog/System Verilog, TCL.

 

2. Familiar with RTL2GDS design flow.

 

3. Understanding of logic design flow.

 

4. Experience of working in Linux system and using of script language

 

5. Good at both written and verbal in English.

 

6. Self-motivation, teamwork and strong communication skills are essential

 

Contact points:

Mr. Blake Huang cwhuangb@qti.qualcomm.com

 

 

 

Website:

 

https://www.104.com.tw/job/6xe8o?jobsource=2018indexpoc

 

https://jobs.qualcomm.com/public/jobDetails.xhtml?requisitionId=1982670